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| author | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 17:43:06 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 17:44:18 +0300 |
| commit | ec38fad35f109a9cd1579977ab149e88e499154f (patch) | |
| tree | f49a5d761f208116359831940beea9fae5ff46b4 /arch/arm64/boot/dts/renesas/r8a77990.dtsi | |
| parent | d0bc18830db34a308e17834ccc480d95a84c1627 (diff) | |
| parent | ee20aeefb53f6ffabed5b1a3b859294197eeb351 (diff) | |
| download | linux-ec38fad35f109a9cd1579977ab149e88e499154f.tar.xz | |
Merge tag 'renesas-arm64-dt2-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt
Second Round of Renesas ARM64 Based SoC DT Updates for v5.1
* R-Car Gen3 SoC based Salvator-X, Salvator-XS and ULCB boards
- Enable HS400 support for eMMC
* R-Car E3 (r7a77990) SoC
- Add OPPs table for cpu devices
* RZ/G2E (r8a774c0) SoC
- Describe TMU, CMT, SDHI devices in DT
- Describe pincontrol support for SCIF2 device in DT
- Add OPPs table for cpu devices
* RZ/G2E (r8a774c0) based EK874 board and CAT875 sub-board,
and CAT874 board
- Initial support
* tag 'renesas-arm64-dt2-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: renesas: cat875: Enable PCIe support
arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support
arm64: dts: renesas: r8a774c0: Add TMU device nodes
arm64: dts: renesas: r8a774c0: Add CMT device nodes
arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices
arm64: dts: renesas: enable HS400 on R-Car Gen3
arm64: dts: renesas: cat875: Add ethernet support
arm64: dts: renesas: r8a774c0-cat874: Add uSD support
arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2
arm64: dts: renesas: Add Si-Linux EK874 board support
arm64: dts: renesas: Add Si-Linux CAT874 board support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a77990.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77990.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 732ead4a94d1..a69faa60ea4d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -55,6 +55,27 @@ clock-frequency = <0>; }; + cluster1_opp: opp_table10 { + compatible = "operating-points-v2"; + opp-shared; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -66,6 +87,8 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@1 { @@ -75,6 +98,8 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA53: cache-controller-0 { |