diff options
| author | Yoshihiro Kaneko <ykaneko0929@gmail.com> | 2018-04-18 23:14:36 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-05-16 11:44:21 +0300 |
| commit | 21559e2b0448cb43e880d46b1381008dc5e9707d (patch) | |
| tree | b0a6314139dd1438b2046a89420cadaf3d76e99d /arch/arm64/boot/dts/renesas/r8a77995.dtsi | |
| parent | 3c3d1672664aff2f7f938d2d206e47cecdf6b4ef (diff) | |
| download | linux-21559e2b0448cb43e880d46b1381008dc5e9707d.tar.xz | |
arm64: dts: renesas: r8a77995: sort subnodes of the root node
Sort subnodes of the root node alphanumerically.
This is part of an ongoing effort to provide consistent node
order in the DT of Renesas SoCs to improve maintainability.
This should not have any run-time effect.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a77995.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77995.dtsi | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 82aed7ee984c..cf476556504a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -18,9 +18,11 @@ #address-cells = <2>; #size-cells = <2>; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; cpus { @@ -51,18 +53,16 @@ clock-frequency = <0>; }; - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; |