diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-10-06 11:58:36 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-10-08 16:16:02 +0300 |
| commit | f28daeedd7f920e172d60a97341be42430175a42 (patch) | |
| tree | 818d67665b5c6b713cb14190e16e1064be4f41b9 /arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | |
| parent | 5de968a25a30302c7714ae1c80b0eaff6834e2ed (diff) | |
| download | linux-f28daeedd7f920e172d60a97341be42430175a42.tar.xz | |
arm64: dts: renesas: falcon-cpu: Add SPI flash via RPC
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211006085836.42155-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index d66e508a2334..cd2f0d60f21a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -203,6 +203,11 @@ power-source = <1800>; }; + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + scif0_pins: scif0 { groups = "scif0_data", "scif0_ctrl"; function = "scif0"; @@ -214,6 +219,34 @@ }; }; +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0xcc0000>; + read-only; + }; + user@cc0000 { + reg = <0xcc0000 0x3340000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; |