diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-08 18:17:42 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-17 10:46:19 +0300 |
| commit | 06279f82da68882b83524385834eeacf1993724f (patch) | |
| tree | ffaa4a30848e06dbfd15bafed9c963fdfef26246 /arch/arm64/boot/dts/renesas/r8a779a0.dtsi | |
| parent | 650fd1d058a161a953f4034acae32471d4b94493 (diff) | |
| download | linux-06279f82da68882b83524385834eeacf1993724f.tar.xz | |
arm64: dts: renesas: r8a779a0: Add CPU0 core clock
Describe the clock for the first Cortex-A76 CPU core.
For now no operating points are defined.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3ace4eea4ff1cdc0f7b8ea7d0433c1063d795785.1654701400.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779a0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 8162ef850376..3d668709d8a8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -41,6 +41,7 @@ device_type = "cpu"; power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76_0>; + clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>; }; L3_CA76_0: cache-controller-0 { |