diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-02-21 18:48:53 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-02-25 16:00:39 +0300 |
| commit | cfcccc9126a7aece5596bb4cba45ba566fd00f0e (patch) | |
| tree | d81be325c1e8537aaa5012867ebb80758a357b7c /arch/arm64/boot/dts/renesas/r8a779f0.dtsi | |
| parent | 6a3b10e5c312cae4c1fc7a27bf9a030360999351 (diff) | |
| download | linux-cfcccc9126a7aece5596bb4cba45ba566fd00f0e.tar.xz | |
arm64: dts: renesas: r8a779f0: Add pinctrl device node
Add a device node for the Pin Function Controller on the Renesas R-Car
S4-8 (R8A779F0) SoC.
Note that the register block does not include registers for banks 4-7,
as they can only be accessed from the Control Domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/cf4d261ba1253879e117f1598b9f47798cbda635.1645458249.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779f0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 0ac8c345558e..f4e549867371 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -69,6 +69,12 @@ status = "disabled"; }; + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a779f0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; |