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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-08 18:40:19 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-17 10:46:19 +0300 |
| commit | ffeca49a8ba9aa39439d30b7bb51f453706b6a0d (patch) | |
| tree | 063312ee667c6fdca5ea5548581d0a5e7bffcb70 /arch/arm64/boot/dts/renesas/r8a779f0.dtsi | |
| parent | 06279f82da68882b83524385834eeacf1993724f (diff) | |
| download | linux-ffeca49a8ba9aa39439d30b7bb51f453706b6a0d.tar.xz | |
arm64: dts: renesas: r8a779f0: Add L3 cache controller
Describe the cache configuration for the first Cortex-A55 CPU core on
the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/a63715ce1d2d2fcc7ab987f7a1b40847965e8d6a.1654701480.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779f0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 54474ba18f5f..a268617587ea 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -23,6 +23,14 @@ reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA55_0>; + }; + + L3_CA55_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; |