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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-14 15:49:02 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-17 22:25:35 +0300 |
| commit | 5bb355a8d62383b1cbc244897bf6c95724ffbf6e (patch) | |
| tree | 62e1af95eef8316b9414aba4d9793514f257f6ca /arch/arm64/boot/dts/renesas/r8a779g0.dtsi | |
| parent | 68c9c53d45fa9c48a89d8a9a4d1555b9e91add69 (diff) | |
| download | linux-5bb355a8d62383b1cbc244897bf6c95724ffbf6e.tar.xz | |
arm64: dts: renesas: r8a779g0: Add CPUIdle support
Support CPUIdle for ARM Cortex-A76 on R-Car V4H.
Based on patches in the BSP by Tho Vu and Vincent Bryce.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f6d4076983eb45cf23595a045747f28cbdcdf4e6.1668429870.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779g0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index dc5f27c114a7..21baa4936b4f 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -45,6 +45,7 @@ power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76_0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_1: cpu@100 { @@ -54,6 +55,7 @@ power-domains = <&sysc R8A779G0_PD_A1E0D0C1>; next-level-cache = <&L3_CA76_0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_2: cpu@10000 { @@ -63,6 +65,7 @@ power-domains = <&sysc R8A779G0_PD_A1E0D1C0>; next-level-cache = <&L3_CA76_1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_3: cpu@10100 { @@ -72,8 +75,22 @@ power-domains = <&sysc R8A779G0_PD_A1E0D1C1>; next-level-cache = <&L3_CA76_1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; + L3_CA76_0: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A779G0_PD_A2E0D0>; |