diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-07 18:20:03 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-17 13:16:52 +0300 |
| commit | a4290d407aa9fd174d8053878783d466d3124e38 (patch) | |
| tree | 466c6358f18a7cea634faab4312a0e4b2b032b6d /arch/arm64/boot/dts/renesas/r8a779g0.dtsi | |
| parent | ab6dc0a22b05199aa3efe2dd79d9b67a00bf01c3 (diff) | |
| download | linux-a4290d407aa9fd174d8053878783d466d3124e38.tar.xz | |
arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock
As serial communication requires a clock signal, the High Speed Serial
Communication Interfaces with FIFO (HSCIF) are clocked by a clock that
is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the clock input for the HSCIF0 Baud Rate Generator internal
clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54.
Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/a5bd4148f92806f7c8e577d383370f810315f586.1665155947.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779g0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index edabd1519ccc..c941054f4980 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -360,7 +360,7 @@ reg = <0 0xe6540000 0 96>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x31>, <&dmac0 0x30>, |