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| author | Duy Nguyen <duy.nguyen.rh@renesas.com> | 2024-02-01 17:19:16 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-22 13:03:32 +0300 |
| commit | 20a942d60b34719df8a145e0364e90981380aefb (patch) | |
| tree | 9ac595edb85f206cd857897bd21cc123df822504 /arch/arm64/boot/dts/renesas/r8a779h0.dtsi | |
| parent | 93e28f88710b2cbe51d6fe760cdf53fc9621f33c (diff) | |
| download | linux-20a942d60b34719df8a145e0364e90981380aefb.tar.xz | |
arm64: dts: renesas: r8a779h0: Add L3 cache controller
Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779h0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index eb555cbf51a4..f47695158d99 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -23,6 +23,14 @@ reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76>; + }; + + L3_CA76: cache-controller { + compatible = "cache"; + power-domains = <&sysc R8A779H0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; |