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| author | Duy Nguyen <duy.nguyen.rh@renesas.com> | 2024-02-01 17:19:19 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-22 13:03:32 +0300 |
| commit | 4c1fd23a220dccaf4b8192d863997213af6e2c31 (patch) | |
| tree | 68d950bde30ca80f8389a03d6cbca7411e962ca5 /arch/arm64/boot/dts/renesas/r8a779h0.dtsi | |
| parent | ad761924be2b33555e7d6b99a0b3b0c8384f549b (diff) | |
| download | linux-4c1fd23a220dccaf4b8192d863997213af6e2c31.tar.xz | |
arm64: dts: renesas: r8a779h0: Add CPU core clocks
Describe the clocks for the four Cortex-A76 CPU cores.
CA76 CPU cores 0,1,2,3 are clocked by ZC0,ZC1,ZC2,ZC3.
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c64cf6ca1590fa1a36b90a18fd70c831d5b8318e.1706796979.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779h0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index b3255bba69e3..622775f6160f 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -43,6 +43,7 @@ next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; }; a76_1: cpu@100 { @@ -53,6 +54,7 @@ next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; }; a76_2: cpu@200 { @@ -63,6 +65,7 @@ next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; }; a76_3: cpu@300 { @@ -73,6 +76,7 @@ next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; }; idle-states { |