diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-25 20:05:21 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-28 17:51:33 +0300 |
| commit | 1de1b44833e394e63119fcff37e458a94c244799 (patch) | |
| tree | 8a6c663748d7d0af52cb100a2218cc06f1c49a1f /arch/arm64/boot/dts/renesas/r9a07g043.dtsi | |
| parent | f52e14095e56ab6470d959f08e40aa2e45cb85cd (diff) | |
| download | linux-1de1b44833e394e63119fcff37e458a94c244799.tar.xz | |
arm64: dts: renesas: r9a07g043: Fillup the CANFD stub node
Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425170530.200921-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g043.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 8bcda969d130..60db9b02e0a7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -291,8 +291,37 @@ }; canfd: can@10050000 { + compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - /* place holder */ + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G043_CANFD_RSTP_N>, + <&cpg R9A07G043_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; }; i2c0: i2c@10058000 { |