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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-05-01 14:29:23 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-06 12:09:33 +0300 |
| commit | e6a9acc370c6cb9e6ff6225b034a7a4374df0134 (patch) | |
| tree | 3e2bdb6a51e770fc63adb1b446de695bb4d12dd9 /arch/arm64/boot/dts/renesas/r9a07g043.dtsi | |
| parent | 22ec868997108e514fe380171c45578da630a0ec (diff) | |
| download | linux-e6a9acc370c6cb9e6ff6225b034a7a4374df0134.tar.xz | |
arm64: dts: renesas: r9a07g043: Add OPP table
Add OPP table for RZ/G2UL SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501112926.47024-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g043.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 82fe61991204..e2300d5c6a15 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -42,6 +42,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -53,6 +80,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { |