diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-11-18 22:18:24 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-26 16:08:19 +0300 |
| commit | 59a7d68b69846ac012c33c1ac425b9388661d1f2 (patch) | |
| tree | 11b5929aa1debcb6c2c4619354aca486e4e1401d /arch/arm64/boot/dts/renesas/r9a07g044.dtsi | |
| parent | 5fcf8b0656cf842ae642298c2874ea6148d0129d (diff) | |
| download | linux-59a7d68b69846ac012c33c1ac425b9388661d1f2.tar.xz | |
arm64: dts: renesas: r9a07g044: Add OSTM nodes
Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211118191826.2026-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g044.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index a7818dbeb271..be9e5c495553 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -791,6 +791,39 @@ power-domains = <&cpg>; status = "disabled"; }; + + ostm0: timer@12801000 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801000 0x0 0x400>; + interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; + resets = <&cpg R9A07G044_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@12801400 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801400 0x0 0x400>; + interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; + resets = <&cpg R9A07G044_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@12801800 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801800 0x0 0x400>; + interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>; + resets = <&cpg R9A07G044_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { |