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authorBiju Das <biju.das.jz@bp.renesas.com>2023-03-15 09:47:26 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2023-03-30 16:56:21 +0300
commit05d11e2f4460752fa5f7ce7657e1b040056c1736 (patch)
treea5fb352e06bdc5dfcb12184709c4c6db34051d8a /arch/arm64/boot/dts/renesas/r9a07g054.dtsi
parent4db0ce4038dec3cf5cb42587a111f4415be381b6 (diff)
downloadlinux-05d11e2f4460752fa5f7ce7657e1b040056c1736.tar.xz
arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes
Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and RZ/Five DMAC nodes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g054.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r9a07g054.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index c0ae9c7c10fc..cc11e5855d62 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -746,9 +746,11 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
+ clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_DMAC_ARESETN>,
<&cpg R9A07G054_DMAC_RST_ASYNC>;
+ reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};