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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2023-04-11 13:03:42 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-05-08 10:16:45 +0300 |
| commit | 79572c7f326ab977e1e9138643e4371067aec844 (patch) | |
| tree | 68805b3a52ebba178c3e6b9c55b0b6f6bb3d1ab3 /arch/arm64/boot/dts/renesas/r9a07g054.dtsi | |
| parent | 9af677e0747965f30b6c3540d464d34e22da5336 (diff) | |
| download | linux-79572c7f326ab977e1e9138643e4371067aec844.tar.xz | |
arm64: dts: renesas: r9a07g054: Add vspd node
Add vspd node to RZ/V2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230411100346.299768-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g054.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index cc75a93caf02..e8ad19fafb53 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -623,6 +623,20 @@ status = "disabled"; }; + vspd: vsp@10870000 { + compatible = "renesas,r9a07g054-vsp2", + "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + fcpvd: fcp@10880000 { compatible = "renesas,r9a07g054-fcpvd", "renesas,fcpv"; |