diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2022-02-27 23:37:37 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-04 12:05:45 +0300 |
| commit | e46a72e0398e570fbab5905ea6be67dc76d678f4 (patch) | |
| tree | 817b4740c03b4ff5702c80984bdb574520441c2a /arch/arm64/boot/dts/renesas/r9a07g054.dtsi | |
| parent | e3ab4573761418ba1b853ec33e5db723db279ff5 (diff) | |
| download | linux-e46a72e0398e570fbab5905ea6be67dc76d678f4.tar.xz | |
arm64: dts: renesas: r9a07g054: Fillup the I2C{0,1,2,3} stub nodes
Fillup the I2C{0,1,2,3} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220227203744.18355-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g054.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 73 |
1 files changed, 70 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 6e89bd126788..fafb986fe3bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -270,22 +270,89 @@ i2c0: i2c@10058000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c1: i2c@10058400 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c3: i2c@10058c00 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; adc: adc@10059000 { |