diff options
| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-01-22 14:11:14 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-31 17:14:23 +0300 |
| commit | cee7bef61f51c04c9946cf4ddb81e85d9c1833d2 (patch) | |
| tree | 956774a0e8ad2d5d43935b7c83cd1776f4283946 /arch/arm64/boot/dts/renesas/r9a08g045.dtsi | |
| parent | 08e799f6bce80dd63c174d8d0fc61d1a6149960b (diff) | |
| download | linux-cee7bef61f51c04c9946cf4ddb81e85d9c1833d2.tar.xz | |
arm64: dts: renesas: r9a08g045: Add watchdog node
Add the DT node for the watchdog IP accessible by Cortex-A of RZ/G3S
SoC (R9108G045).
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240122111115.2861835-10-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a08g045.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 5facfad96158..dfee878c0f49 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -264,6 +264,20 @@ <0x0 0x12440000 0 0x60000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G045_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G045_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { |