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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-11-10 19:09:31 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-15 11:40:10 +0300 |
| commit | c6b1737f45ca708fee76a30afb4a7b0247455749 (patch) | |
| tree | 9dc5e71440e4c2badfc599a9eb7482c6c464c9dc /arch/arm64/boot/dts/renesas/r9a09g011.dtsi | |
| parent | 594edf2c61f2eb79234e642e3a82d7ae02e7a241 (diff) | |
| download | linux-c6b1737f45ca708fee76a30afb4a7b0247455749.tar.xz | |
arm64: dts: renesas: r9a09g011: Add L2 Cache node
The Cortex-A53 processor on RZ/V2M has 512 KB L2 Cache.
Add L2 Cache node to SoC dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221110160931.101539-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a09g011.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 2ccd48ee9880..ca9f022d6632 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -37,8 +37,15 @@ compatible = "arm,cortex-a53"; reg = <0>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; }; + + L2_CA53: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; }; soc: soc { |