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authorBiju Das <biju.das.jz@bp.renesas.com>2021-12-16 14:43:04 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2022-01-24 12:00:36 +0300
commit3a3c2a48d8c6ba586a2eda249b0e2f5f19609dfd (patch)
tree97641467545bcea86a01a975cf0f41ddf4db98a8 /arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
parent65d2bc885b01642bbd0898b8af573783ab84f835 (diff)
downloadlinux-3a3c2a48d8c6ba586a2eda249b0e2f5f19609dfd.tar.xz
arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC
The RZ/G2L and RZ/G2LC SoCs are similar and they share the same DEVID. RZ/G2LC has fewer peripherals compared to RZ/G2L. SSI (3 channels vs 4 channels) GbEthernet (1 channel vs 2 channels) SCIFA (4 channels vs 5 channels) ADC is only supported in RZ/G2L. Add the initial DTSI for the RZ/G2LC SoC by reusing the common r9a07g044.dtsi file with unsupported device nodes deleted in the below SoC specific dtsi files. r9a07g044c1.dtsi => RZ/G2LC R9A07G044C1 SoC specific parts r9a07g044c2.dtsi => RZ/G2LC R9A07G044C2 SoC specific parts Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211216114305.5842-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi')
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