diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-02-03 20:06:35 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-02-08 11:45:59 +0300 |
| commit | fa00d6dc19283bee13f0390546f741293f6d2d9a (patch) | |
| tree | 1408bd53ae1cecd295f9a42debd64c4ac4659713 /arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | |
| parent | 2ed3b5d9540b246d7a1ec98971914ee810b40086 (diff) | |
| download | linux-fa00d6dc19283bee13f0390546f741293f6d2d9a.tar.xz | |
arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board
SCIF1 interface is available on PMOD1 connector (CN7) on carrier board.
This patch adds pinmux and scif1 node to carrier board dtsi file for
RZ/G2LC SMARC EVK.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220203170636.7747-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index ca5ca7ce6692..1b59ef376296 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -34,3 +34,29 @@ #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" + +/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/ { + aliases { + serial1 = &scif1; + }; +}; + +/* + * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board + * SW1 should be at position 2->3 so that SER0_CTS# line is activated + * SW2 should be at position 2->3 so that SER0_TX line is activated + * SW3 should be at position 2->3 so that SER0_RX line is activated + * SW4 should be at position 2->3 so that SER0_RTS# line is activated + */ +#if (!SW_SCIF_CAN && PMOD1_SER0) +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; +#endif |