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| author | Bhavya Kapoor <b-kapoor@ti.com> | 2023-12-01 11:20:43 +0300 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2023-12-15 19:05:58 +0300 |
| commit | 908999561b4340089896b89cef51dae07fc001cb (patch) | |
| tree | 2ebd9ffe13a9f3b4a562ba9cef0438e0914e5b10 /arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | |
| parent | 7643f7ebcbc723e682d22c207ac35b41d7248650 (diff) | |
| download | linux-908999561b4340089896b89cef51dae07fc001cb.tar.xz | |
arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode
DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value
is not present in the device tree. Thus, add Itap Delay Value for eMMC
High Speed DDR which is DDR52 speed mode for J7200 SoC according to
datasheet for J7200.
[+] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface, in
J7200 datasheet
- https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Judith Mendez <jm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20231201082045.790478-2-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j7200-main.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index b8424994ac5f..da67bf8fe703 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -651,6 +651,7 @@ ti,otap-del-sel-hs400 = <0x5>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; ti,strobe-sel = <0x77>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; |