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author | Tony Lindgren <tony@atomide.com> | 2023-11-24 11:50:56 +0300 |
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committer | Tony Lindgren <tony@atomide.com> | 2023-11-28 13:57:16 +0300 |
commit | f71f6ff8c1f682a1cae4e8d7bdeed9d7f76b8f75 (patch) | |
tree | ae375ae58c46d03bd14a1d203933349abe895d7f /arch/arm | |
parent | b85ea95d086471afb4ad062012a4d73cd328fa86 (diff) | |
download | linux-f71f6ff8c1f682a1cae4e8d7bdeed9d7f76b8f75.tar.xz |
bus: ti-sysc: Flush posted write only after srst_udelay
Commit 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before
reset") caused a regression reproducable on omap4 duovero where the ISS
target module can produce interconnect errors on boot. Turns out the
registers are not accessible until after a delay for devices needing
a ti,sysc-delay-us value.
Let's fix this by flushing the posted write only after the reset delay.
We do flushing also for ti,sysc-delay-us using devices as that should
trigger an interconnect error if the delay is not properly configured.
Let's also add some comments while at it.
Fixes: 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before reset")
Cc: stable@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
0 files changed, 0 insertions, 0 deletions