diff options
author | Jaedon Shin <jaedon.shin@gmail.com> | 2017-11-17 05:19:42 +0300 |
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committer | James Hogan <jhogan@kernel.org> | 2018-03-06 03:24:11 +0300 |
commit | c7146a2b5892ce97b71a66a47b0f6106a4a444e3 (patch) | |
tree | de7ab80d692907b789f097c5a43cb7c807380a7f /arch/mips/boot/dts/brcm/bcm7360.dtsi | |
parent | cccd0b9a72d27f681c2e45da0c263a46e5c63926 (diff) | |
download | linux-c7146a2b5892ce97b71a66a47b0f6106a4a444e3.tar.xz |
MIPS: BMIPS: Add Broadcom STB power management nodes
Adds power management nodes to BCM7xxx MIPS based SoCs.
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17727/
Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'arch/mips/boot/dts/brcm/bcm7360.dtsi')
-rw-r--r-- | arch/mips/boot/dts/brcm/bcm7360.dtsi | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi index 4b87ebec407a..f68285c2dff0 100644 --- a/arch/mips/boot/dts/brcm/bcm7360.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi @@ -219,6 +219,17 @@ brcm,irq-can-wake; }; + aon_ctrl: syscon@408000 { + compatible = "brcm,brcmstb-aon-ctrl"; + reg = <0x408000 0x100>, <0x408200 0x200>; + reg-names = "aon-ctrl", "aon-sram"; + }; + + timers: timer@406680 { + compatible = "brcm,brcmstb-timers"; + reg = <0x406680 0x40>; + }; + upg_gio: gpio@406500 { compatible = "brcm,brcmstb-gpio"; reg = <0x406500 0xa0>; @@ -403,4 +414,38 @@ status = "disabled"; }; }; + + memory_controllers { + compatible = "simple-bus"; + ranges = <0x0 0x103b0000 0xa000>; + #address-cells = <1>; + #size-cells = <1>; + + memory-controller@0 { + compatible = "brcm,brcmstb-memc", "simple-bus"; + ranges = <0x0 0x0 0xa000>; + #address-cells = <1>; + #size-cells = <1>; + + memc-arb@1000 { + compatible = "brcm,brcmstb-memc-arb"; + reg = <0x1000 0x248>; + }; + + memc-ddr@2000 { + compatible = "brcm,brcmstb-memc-ddr"; + reg = <0x2000 0x300>; + }; + + ddr-phy@6000 { + compatible = "brcm,brcmstb-ddr-phy"; + reg = <0x6000 0xc8>; + }; + + shimphy@8000 { + compatible = "brcm,brcmstb-ddr-shimphy"; + reg = <0x8000 0x13c>; + }; + }; + }; }; |