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| author | Dario Binacchi <dario.binacchi@amarulasolutions.com> | 2023-11-24 13:02:37 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2023-12-01 13:15:33 +0300 |
| commit | a9e1e4d6e8c77c732e8084b03bae0c78cafdceb0 (patch) | |
| tree | 27371d86ed904faa53282c33647f0ed06174e931 /arch/powerpc/platforms/85xx/mpc85xx_rdb.c | |
| parent | e12d8e2602d2bcd26022eff3e2519d25925e760c (diff) | |
| download | linux-a9e1e4d6e8c77c732e8084b03bae0c78cafdceb0.tar.xz | |
powerpc/85xx: Fix typo in code comment
s/singals/signals/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20231124100241.660374-1-dario.binacchi@amarulasolutions.com
Diffstat (limited to 'arch/powerpc/platforms/85xx/mpc85xx_rdb.c')
| -rw-r--r-- | arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index ec9f60fbebc7..e0cec670d8db 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -76,7 +76,7 @@ static void __init mpc85xx_rdb_setup_arch(void) /* P1025 has pins muxed for QE and other functions. To * enable QE UEC mode, we need to set bit QE0 for UCC1 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 - * and QE12 for QE MII management singals in PMUXCR + * and QE12 for QE MII management signals in PMUXCR * register. */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | |