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| author | Conor Dooley <conor.dooley@microchip.com> | 2023-10-09 12:37:47 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-10-15 15:16:05 +0300 |
| commit | 81b5948cf1a7ad49ba72fa0674710bd3f44deb9e (patch) | |
| tree | 53211726f92f257c0a8fd40eaa8356940cc7e2f4 /arch/riscv/boot/dts/starfive/jh7100.dtsi | |
| parent | a54f42722e494c86ad0eeba198a662d68aeabb15 (diff) | |
| download | linux-81b5948cf1a7ad49ba72fa0674710bd3f44deb9e.tar.xz | |
riscv: dts: starfive: convert isa detection to new properties
Convert the jh7100 and jh7110 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot/dts/starfive/jh7100.dtsi')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 35ab54fb235f..e68cafe7545f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -33,6 +33,9 @@ i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu0_intc: interrupt-controller { @@ -58,6 +61,9 @@ i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { |