diff options
| author | Peter Zijlstra <peterz@infradead.org> | 2022-05-11 17:27:06 +0300 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-05-11 17:27:06 +0300 |
| commit | 47319846a9e2ab1c4d22108e891818d003615bd8 (patch) | |
| tree | 919dbed5c01d3ad4db009bd38bb12cfd3d038246 /arch/x86/include/asm/msr-index.h | |
| parent | 3d47083b9ff46863e8374ad3bb5edb5e464c75f8 (diff) | |
| parent | 672c0c5173427e6b3e2a9bbb7be51ceeec78093a (diff) | |
| download | linux-47319846a9e2ab1c4d22108e891818d003615bd8.tar.xz | |
Merge branch 'v5.18-rc5'
Obtain the new INTEL_FAM6 stuff required.
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 58a44dceef9a..cf4ce6aeba67 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -128,9 +128,9 @@ #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ -/* SRBDS support */ #define MSR_IA32_MCU_OPT_CTRL 0x00000123 -#define RNGDS_MITG_DIS BIT(0) +#define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ +#define RTM_ALLOW BIT(1) /* TSX development mode */ #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 |