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| author | H. Peter Anvin (Intel) <hpa@zytor.com> | 2023-01-12 10:20:32 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2023-01-13 12:07:27 +0300 |
| commit | 92cbbadf73f45c5d8bb26ed8668ff59671ff21e6 (patch) | |
| tree | af1ce62216d2f0aa7051471fa8704f14a4288b06 /arch/x86/xen | |
| parent | ae53fa18703000f507107df43efd1168a0365361 (diff) | |
| download | linux-92cbbadf73f45c5d8bb26ed8668ff59671ff21e6.tar.xz | |
x86/gsseg: Use the LKGS instruction if available for load_gs_index()
The LKGS instruction atomically loads a segment descriptor into the
%gs descriptor registers, *except* that %gs.base is unchanged, and the
base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
what we want this function to do.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230112072032.35626-6-xin3.li@intel.com
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/x86/xen')
| -rw-r--r-- | arch/x86/xen/enlighten_pv.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 5b1379662877..ce2f19ee4bfc 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -276,6 +276,7 @@ static void __init xen_init_capabilities(void) setup_clear_cpu_cap(X86_FEATURE_ACC); setup_clear_cpu_cap(X86_FEATURE_X2APIC); setup_clear_cpu_cap(X86_FEATURE_SME); + setup_clear_cpu_cap(X86_FEATURE_LKGS); /* * Xen PV would need some work to support PCID: CR3 handling as well |