diff options
| author | Paul Cercueil <paul@crapouillou.net> | 2021-05-30 19:49:21 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-06-28 05:49:17 +0300 |
| commit | 037f1ffd0f0a6bad89e17aa4698c97ef430c6ad1 (patch) | |
| tree | a9bfcfae8cfa961c5caba6119ec444bd857be429 /drivers/clk/ingenic/jz4770-cgu.c | |
| parent | 315a8423b20362bb675c5263cb237ecb51d9589e (diff) | |
| download | linux-037f1ffd0f0a6bad89e17aa4698c97ef430c6ad1.tar.xz | |
clk: ingenic: Remove pll_info.no_bypass_bit
We can express that a PLL has no bypass bit by simply setting the
.bypass_bit field to a negative value.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/jz4770-cgu.c')
| -rw-r--r-- | drivers/clk/ingenic/jz4770-cgu.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 381a27f20b51..2321742b3471 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -139,8 +139,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, - .bypass_reg = CGU_REG_CPPCR1, - .no_bypass_bit = true, + .bypass_bit = -1, .enable_bit = 7, .stable_bit = 6, }, |