diff options
| author | Chen Zhong <chen.zhong@mediatek.com> | 2017-10-05 06:50:23 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-11-02 11:07:51 +0300 |
| commit | c955bf3998efa3355790a4d8c82874582f1bc727 (patch) | |
| tree | 4df4e73b5bd0d3d4ba1405bdb20950b7b5070308 /drivers/clk/mediatek/clk-pll.c | |
| parent | 808ecf4ad087f80c2eee99af67549f05d5315694 (diff) | |
| download | linux-c955bf3998efa3355790a4d8c82874582f1bc727.tar.xz | |
clk: mediatek: add the option for determining PLL source clock
Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.
Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-pll.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-pll.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 3c546bae6955..f54e4015b0b1 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -312,7 +312,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, init.name = data->name; init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; init.ops = &mtk_pll_ops; - init.parent_names = &parent_name; + if (data->parent_name) + init.parent_names = &data->parent_name; + else + init.parent_names = &parent_name; init.num_parents = 1; clk = clk_register(NULL, &pll->hw); |