diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-02-06 13:00:59 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-03-13 21:46:23 +0300 |
| commit | 8da312d6574c7b3f58ee8dbc85afa392224b5470 (patch) | |
| tree | 56c7b12ebeb82ba32cdb0b02cf76b86b0589670e /drivers/clk/mediatek/clk-pllfh.h | |
| parent | fe15c26ee26efa11741a7b632e9f23b01aca4cc6 (diff) | |
| download | linux-8da312d6574c7b3f58ee8dbc85afa392224b5470.tar.xz | |
clk: mediatek: fhctl: Add support for older fhctl register layout
The Frequency Hopping Controller (FHCTL) seems to have different
versions, as it has a slightly different register layout on some
older SoCs like MT6795, MT8173, MT8183 (and others).
This driver is indeed compatible with at least some of those older
IP revisions, so all we need to do is to add a way to select the
right register layout at registration time.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-2-angelogioacchino.delregno@collabora.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-pllfh.h')
| -rw-r--r-- | drivers/clk/mediatek/clk-pllfh.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pllfh.h index c0a6e1537034..5f419c2ec01f 100644 --- a/drivers/clk/mediatek/clk-pllfh.h +++ b/drivers/clk/mediatek/clk-pllfh.h @@ -18,6 +18,7 @@ struct fh_pll_state { struct fh_pll_data { int pll_id; int fh_id; + int fh_ver; u32 fhx_offset; u32 dds_mask; u32 slope0_value; |