diff options
author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-03-26 15:00:58 +0300 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-05-11 10:57:06 +0300 |
commit | 50086045bd07a9bc55c113f2b19a8f3746c9f9b0 (patch) | |
tree | aab69c05c1394a1adefd7884bfbb1ba06ead189d /drivers/clk/renesas/rcar-gen3-cpg.c | |
parent | 67a1b9b65165bd3204adef13f0d557b5705116b4 (diff) | |
download | linux-50086045bd07a9bc55c113f2b19a8f3746c9f9b0.tar.xz |
clk: renesas: rcar-gen3: Increase Z clock accuracy
Improve accuracy in the .determine_rate() callback for Z and Z2 clocks
by using rounded divisions. This is similar to the calculation of rates
and multipliers in the .recalc_rate() resp. set_rate() callbacks.
Sample impact for a few requested clock rates:
- R-Car H3:
- Z 500 MHz: 468 MHz => 515 MHz
- Z2 1000 MHz: 973 MHz => 1011 MHz
- R-Car M3-W:
- Z 500 MHz: 422 MHz => 516 MHz
- Z2 800 MHz: 750 MHz => 788 MHz
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-6-geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
-rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index a241bf6e904f..6b389c1caca7 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -83,10 +83,10 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw, if (max_mult < min_mult) return -EINVAL; - mult = div64_ul(req->rate * 32ULL, prate); + mult = DIV_ROUND_CLOSEST_ULL(req->rate * 32ULL, prate); mult = clamp(mult, min_mult, max_mult); - req->rate = div_u64((u64)prate * mult, 32); + req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); return 0; } |