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| author | Derek Basehore <dbasehore@chromium.org> | 2018-03-13 23:37:19 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-03-14 02:37:22 +0300 |
| commit | 4ee3fd4abeca30d530fe67972f1964f7454259d6 (patch) | |
| tree | 466579a6610cb0f25a0b836c27dad771367c36aa /drivers/clk/rockchip/clk-rk3228.c | |
| parent | 60cf09e45fbcbbbb3162f02e0923a25ae7f5627e (diff) | |
| download | linux-4ee3fd4abeca30d530fe67972f1964f7454259d6.tar.xz | |
clk: rockchip: Add 1.6GHz PLL rate for rk3399
We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3228.c')
0 files changed, 0 insertions, 0 deletions