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authorElaine Zhang <zhangqing@rock-chips.com>2017-08-21 11:16:05 +0300
committerHeiko Stuebner <heiko@sntech.de>2017-08-22 03:50:45 +0300
commit100542725f605d4399536eb162c036977996b5cc (patch)
tree52385518826cc60e53d548504f2cf5ab3fb2245b /drivers/clk/rockchip/clk-rv1108.c
parentfe53230cf22644e187d688f65e295ad61d9169cf (diff)
downloadlinux-100542725f605d4399536eb162c036977996b5cc.tar.xz
clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks
Add gmac aclk and pclk clock gates. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-rv1108.c')
-rw-r--r--drivers/clk/rockchip/clk-rv1108.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
index d1065dd9f442..0e441ec21e90 100644
--- a/drivers/clk/rockchip/clk-rv1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -763,6 +763,8 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
GATE(SCLK_MACPHY_RX, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
+ GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
+ GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),