diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2021-03-03 00:41:51 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-03-31 05:26:26 +0300 |
| commit | ba7e258425acd8587b62196e3f00f62c0f7625d0 (patch) | |
| tree | 0b13fd13e65382ff8ff6fb743e5bece3b35b9e86 /drivers/clk/socfpga/clk-pll-s10.c | |
| parent | 8c489216c3e103a24856fd676fc5f51619c2e052 (diff) | |
| download | linux-ba7e258425acd8587b62196e3f00f62c0f7625d0.tar.xz | |
clk: socfpga: Convert to s10/agilex/n5x to use clk_hw
As recommended by Stephen Boyd, convert the Agilex/Stratix10/n5x clock
driver to use the clk_hw registration method.
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210302214151.1333447-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-pll-s10.c')
| -rw-r--r-- | drivers/clk/socfpga/clk-pll-s10.c | 43 |
1 files changed, 25 insertions, 18 deletions
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index f6f66e08e1f4..bc37461d43c0 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -187,13 +187,14 @@ static const struct clk_ops clk_boot_ops = { .prepare = clk_pll_prepare, }; -struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, +struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks, void __iomem *reg) { - struct clk *clk; + struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; struct clk_init_data init; const char *name = clks->name; + int ret; pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); if (WARN_ON(!pll_clk)) @@ -216,21 +217,24 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; - clk = clk_register(NULL, &pll_clk->hw.hw); - if (WARN_ON(IS_ERR(clk))) { + hw_clk = &pll_clk->hw.hw; + + ret = clk_hw_register(NULL, hw_clk); + if (ret) { kfree(pll_clk); - return NULL; + return ERR_PTR(ret); } - return clk; + return hw_clk; } -struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks, +struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks, void __iomem *reg) { - struct clk *clk; + struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; struct clk_init_data init; const char *name = clks->name; + int ret; pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); if (WARN_ON(!pll_clk)) @@ -252,22 +256,24 @@ struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; + hw_clk = &pll_clk->hw.hw; - clk = clk_register(NULL, &pll_clk->hw.hw); - if (WARN_ON(IS_ERR(clk))) { + ret = clk_hw_register(NULL, hw_clk); + if (ret) { kfree(pll_clk); - return NULL; + return ERR_PTR(ret); } - return clk; + return hw_clk; } -struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks, +struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks, void __iomem *reg) { - struct clk *clk; + struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; struct clk_init_data init; const char *name = clks->name; + int ret; pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); if (WARN_ON(!pll_clk)) @@ -289,11 +295,12 @@ struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; + hw_clk = &pll_clk->hw.hw; - clk = clk_register(NULL, &pll_clk->hw.hw); - if (WARN_ON(IS_ERR(clk))) { + ret = clk_hw_register(NULL, hw_clk); + if (ret) { kfree(pll_clk); - return NULL; + return ERR_PTR(ret); } - return clk; + return hw_clk; } |