diff options
| author | Marco Chiappero <marco.chiappero@intel.com> | 2021-09-28 14:44:33 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2021-10-08 15:02:41 +0300 |
| commit | b79c7532dc337c87365fda62914eaeb0e038160d (patch) | |
| tree | d43b45a53b1262ee38d71fca686349113d90b21b /drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h | |
| parent | 993161d36ab5f0f8064751f157482d332a8fcf2c (diff) | |
| download | linux-b79c7532dc337c87365fda62914eaeb0e038160d.tar.xz | |
crypto: qat - remove duplicated logic across GEN2 drivers
QAT GEN2 devices share most of the behavior which means a number of
device specific functions can be shared too and some differences
abstracted away by simple parameters.
The functions adf_enable_error_correction(), get_num_accels(),
get_num_aes() and get_pf2vf_offset() for c3xxx, c62x and dh895xx have
been reworked and moved to the GEN2 file, adf_gen2_hw_data.c.
The definitions of tx_rx_gap and tx_rings_mask have been moved to
adf_gen2_hw_data.h.
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h')
| -rw-r--r-- | drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h index 0f9f24b44663..0af34dd8708a 100644 --- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h +++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h @@ -7,8 +7,6 @@ #define ADF_DH895XCC_SRAM_BAR 0 #define ADF_DH895XCC_PMISC_BAR 1 #define ADF_DH895XCC_ETR_BAR 2 -#define ADF_DH895XCC_RX_RINGS_OFFSET 8 -#define ADF_DH895XCC_TX_RINGS_MASK 0xFF #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000 #define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0 @@ -25,19 +23,10 @@ #define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) #define ADF_DH895XCC_SMIA0_MASK 0xFFFFFFFF #define ADF_DH895XCC_SMIA1_MASK 0x1 -/* Error detection and correction */ -#define ADF_DH895XCC_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) -#define ADF_DH895XCC_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) -#define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28) -#define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) -#define ADF_DH895XCC_UERRSSMSH(i) (i * 0x4000 + 0x18) -#define ADF_DH895XCC_CERRSSMSH(i) (i * 0x4000 + 0x10) -#define ADF_DH895XCC_ERRSSMSH_EN BIT(3) /* Masks for VF2PF interrupts */ #define ADF_DH895XCC_ERR_REG_VF2PF_U(vf_src) (((vf_src) & 0x0000FFFF) << 16) #define ADF_DH895XCC_ERR_MSK_VF2PF_U(vf_mask) ((vf_mask) >> 16) -#define ADF_DH895XCC_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04)) /* AE to function mapping */ #define ADF_DH895XCC_AE2FUNC_MAP_GRP_A_NUM_REGS 96 |