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authorRobert Richter <rrichter@amd.com>2023-10-18 20:16:58 +0300
committerDan Williams <dan.j.williams@intel.com>2023-10-28 06:13:37 +0300
commit4d758764e7f9db83806135f3bfcff1ab64f16e60 (patch)
treefe3e73cb06fadd8f540a584a13c18c079c51996a /drivers/cxl/core
parentd8add49263a98d766e5758dc2ec9f83c3b685c12 (diff)
downloadlinux-4d758764e7f9db83806135f3bfcff1ab64f16e60.tar.xz
cxl/port: Pre-initialize component register mappings
The component registers of a component may not exist and cxl_setup_comp_regs() will fail for that reason. In another case, Software may not use and set those registers up. cxl_setup_comp_regs() is then called with a base address of CXL_RESOURCE_NONE. Both are valid cases, but the function returns without initializing the register map. Now, a missing component register block is not necessarily a reason to fail (feature is optional or its existence checked later). Change cxl_setup_comp_regs() to also use components with the component register block missing. Thus, always initialize struct cxl_register_map with valid values, set @dev and make @resource CXL_RESOURCE_NONE. The change is in preparation of follow-on patches. Signed-off-by: Terry Bowman <terry.bowman@amd.com> Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20231018171713.1883517-6-rrichter@amd.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/core')
-rw-r--r--drivers/cxl/core/port.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index f6ced15dbf73..252aa3dc96e2 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -694,16 +694,18 @@ err:
static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map,
resource_size_t component_reg_phys)
{
- if (component_reg_phys == CXL_RESOURCE_NONE)
- return 0;
-
*map = (struct cxl_register_map) {
.host = host,
- .reg_type = CXL_REGLOC_RBI_COMPONENT,
+ .reg_type = CXL_REGLOC_RBI_EMPTY,
.resource = component_reg_phys,
- .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
};
+ if (component_reg_phys == CXL_RESOURCE_NONE)
+ return 0;
+
+ map->reg_type = CXL_REGLOC_RBI_COMPONENT;
+ map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
+
return cxl_setup_regs(map);
}