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| author | Dan Williams <dan.j.williams@intel.com> | 2023-10-31 20:59:26 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-10-31 20:59:26 +0300 |
| commit | 624eda92abd47f35386028e4a54d423037a75d12 (patch) | |
| tree | 15fb6ca0683ce93bb4077009865b53a79b2e94ae /drivers/cxl/cxl.h | |
| parent | 7f946e6d830fbdf411cd0641314edf11831efc88 (diff) | |
| parent | a103f46633fdcddc2aaca506420f177e8803a2bd (diff) | |
| download | linux-624eda92abd47f35386028e4a54d423037a75d12.tar.xz | |
Merge branch 'for-6.7/cxl-qtg' into cxl/next
Merge some prep-work for CXL QOS class support. This cycle saw large
collisions with mm on this topic, so the bulk of this topic needs to
wait.
Diffstat (limited to 'drivers/cxl/cxl.h')
| -rw-r--r-- | drivers/cxl/cxl.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 378fc96ff7ff..02d307fa793a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -328,6 +328,7 @@ enum cxl_decoder_type { */ #define CXL_DECODER_MAX_INTERLEAVE 16 +#define CXL_QOS_CLASS_INVALID -1 /** * struct cxl_decoder - Common CXL HDM Decoder Attributes @@ -439,6 +440,7 @@ typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, * @calc_hb: which host bridge covers the n'th position by granularity * @platform_data: platform specific configuration data * @range_lock: sync region autodiscovery by address range + * @qos_class: QoS performance class cookie * @cxlsd: base cxl switch decoder */ struct cxl_root_decoder { @@ -447,6 +449,7 @@ struct cxl_root_decoder { cxl_calc_hb_fn calc_hb; void *platform_data; struct mutex range_lock; + int qos_class; struct cxl_switch_decoder cxlsd; }; |