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| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 02:34:48 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 18:50:41 +0300 |
| commit | 14d78874077442d1d0f08129f5a0ea5070984b4b (patch) | |
| tree | 4c80ac1f7f8fb934b3a430fdcdacee9d40e47f05 /drivers/cxl/cxlmem.h | |
| parent | 2e4ba0ec978335b4b550bbed95cb198ac3a00745 (diff) | |
| download | linux-14d78874077442d1d0f08129f5a0ea5070984b4b.tar.xz | |
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
In preparation for fixing the setting of the 'mem_enabled' bit in CXL
DVSEC Control register, move all CXL DVSEC range enumeration into the
same source file.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291688886.1426646.15046138604010482084.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxlmem.h')
| -rw-r--r-- | drivers/cxl/cxlmem.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 843916c1dab6..60d10ee1e7fc 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -222,7 +222,6 @@ struct cxl_dev_state { u64 next_persistent_bytes; resource_size_t component_reg_phys; - struct cxl_endpoint_dvsec_info info; u64 serial; int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); |