drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h

DC needs to include the soc bounding box when initializing HW resources.

Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is
required to define amdgpu_device. The solution here is to split the
bounding box structs into a different header, then include it in both
amdgpu_ucode.h, and relevant DC HW resource files.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 2 insertions, 56 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 52b024917075..f46944453c6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -23,6 +23,8 @@
 #ifndef __AMDGPU_UCODE_H__
 #define __AMDGPU_UCODE_H__
 
+#include "amdgpu_socbb.h"
+
 struct common_firmware_header {
 	uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
 	uint32_t header_size_bytes; /* size of just the header in bytes */
@@ -210,62 +212,6 @@ struct gpu_info_firmware_v1_1 {
 	uint32_t num_packer_per_sc;
 };
 
-struct gpu_info_voltage_scaling_v1_0 {
-	int state;
-	uint32_t dscclk_mhz;
-	uint32_t dcfclk_mhz;
-	uint32_t socclk_mhz;
-	uint32_t dram_speed_mts;
-	uint32_t fabricclk_mhz;
-	uint32_t dispclk_mhz;
-	uint32_t phyclk_mhz;
-	uint32_t dppclk_mhz;
-};
-
-struct gpu_info_soc_bounding_box_v1_0 {
-	uint32_t sr_exit_time_us;
-	uint32_t sr_enter_plus_exit_time_us;
-	uint32_t urgent_latency_us;
-	uint32_t urgent_latency_pixel_data_only_us;
-	uint32_t urgent_latency_pixel_mixed_with_vm_data_us;
-	uint32_t urgent_latency_vm_data_only_us;
-	uint32_t writeback_latency_us;
-	uint32_t ideal_dram_bw_after_urgent_percent;
-	uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
-	uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
-	uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;
-	uint32_t max_avg_sdp_bw_use_normal_percent;
-	uint32_t max_avg_dram_bw_use_normal_percent;
-	unsigned int max_request_size_bytes;
-	uint32_t downspread_percent;
-	uint32_t dram_page_open_time_ns;
-	uint32_t dram_rw_turnaround_time_ns;
-	uint32_t dram_return_buffer_per_channel_bytes;
-	uint32_t dram_channel_width_bytes;
-	uint32_t fabric_datapath_to_dcn_data_return_bytes;
-	uint32_t dcn_downspread_percent;
-	uint32_t dispclk_dppclk_vco_speed_mhz;
-	uint32_t dfs_vco_period_ps;
-	unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
-	unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
-	unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
-	unsigned int round_trip_ping_latency_dcfclk_cycles;
-	unsigned int urgent_out_of_order_return_per_channel_bytes;
-	unsigned int channel_interleave_bytes;
-	unsigned int num_banks;
-	unsigned int num_chans;
-	unsigned int vmm_page_size_bytes;
-	uint32_t dram_clock_change_latency_us;
-	uint32_t writeback_dram_clock_change_latency_us;
-	unsigned int return_bus_width_bytes;
-	unsigned int voltage_override;
-	uint32_t xfc_bus_transport_time_us;
-	uint32_t xfc_xbuf_latency_tolerance_us;
-	int use_urgent_burst_bw;
-	unsigned int num_states;
-	struct gpu_info_voltage_scaling_v1_0 clock_limits[8];
-};
-
 /* gpu info payload
  * version_major=1, version_minor=1 */
 struct gpu_info_firmware_v1_2 {