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| author | Hamza Mahfooz <hamza.mahfooz@amd.com> | 2023-03-21 23:35:28 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-04-12 01:03:35 +0300 |
| commit | 6f6869dcf415f7c222057a3f07c23667e1758585 (patch) | |
| tree | 80a0eadc798497736c17a857f3ae5f25d16b41d2 /drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | |
| parent | 0efa70356882ec2a843122f02892391ae61fc4d3 (diff) | |
| download | linux-6f6869dcf415f7c222057a3f07c23667e1758585.tar.xz | |
drm/amd/display: prep work for root clock optimization enablement for DCN314
To enable root clock optimizations, we need a number of
register writes and need to account for the difference
in DPSTREAMCLK between DCN31 and DCN314. To prevent
issues, add a number of register writes to
DCCG_MASK_SH_LIST_DCN314_COMMON(), and define dccg314_init()
which is mostly in alignment with dccg31_init() but
accounts for the new DPSTREAMCLK sequence.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c')
0 files changed, 0 insertions, 0 deletions