diff options
| author | Chris Park <Chris.Park@amd.com> | 2020-06-10 06:51:36 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 08:59:26 +0300 |
| commit | 5e90801298cc5c7ac7fac7d5fb0705e7bedf1eea (patch) | |
| tree | 3f32cf836415c06c9b16f94d8e8a23e9a3fb3999 /drivers/gpu/drm/amd | |
| parent | 7715fdf3362fa88f3e3620261a6e546f50713a5e (diff) | |
| download | linux-5e90801298cc5c7ac7fac7d5fb0705e7bedf1eea.tar.xz | |
drm/amd/display: Allow 4 split on 10K 420 modes
[Why]
10K YCbCr420 does not need ODM 4:1, but it requires MPC 4 split
indicated on the flags.
[How]
Make pixel encoding and resolution size specific workaround to enable
ODM combine on YCbCr420 high resolution modes.
Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 5 |
2 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index d3be19b1d0ab..0983bcc25117 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2745,6 +2745,11 @@ int dcn20_validate_apply_pipe_split_flags( split[i] = 4; v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; } + /*420 format workaround*/ + if (pipe->stream->timing.h_addressable > 7680 && + pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + split[i] = 4; + } #endif v->ODMCombineEnabled[pipe_plane] = v->ODMCombineEnablePerState[vlevel][pipe_plane]; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 5909af0a25fb..75dc4fe41731 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -3986,11 +3986,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) { v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; - /*420 format workaround*/ - if (v->HActive[k] > 7680 && v->OutputFormat[k] == dm_420) { - v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; - v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1; - } } else { v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine; |