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authorStefan Agner <stefan@agner.ch>2016-01-15 04:24:29 +0300
committerStefan Agner <stefan@agner.ch>2016-02-26 03:13:16 +0300
commitf76b9873d7db0afb51f2df389a99284ef484b86f (patch)
treee4258bfb255fd5d35c430c8508548c10f83ea2d8 /drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
parent4bc390c6337b6c73e0b44895e0ade7212f2815bf (diff)
downloadlinux-f76b9873d7db0afb51f2df389a99284ef484b86f.tar.xz
drm/fsl-dcu: fix register initialization
The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for Vybrid) whereas the register enumeration start from 1 (1-10 for LS1021a and 1-9 for Vybrid). The loop started off from 0 for both iterations and initialized the number of layers inclusive, which is one layer too many. All extensively written registers seem to be unassigned, it seems that the write to those registers did not do any harm in practice. Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c')
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index b36f815bd1d8..7574db2da413 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -164,8 +164,8 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
reg_num = LS1021A_LAYER_REG_NUM;
else
reg_num = VF610_LAYER_REG_NUM;
- for (i = 0; i <= fsl_dev->soc->total_layer; i++) {
- for (j = 0; j < reg_num; j++)
+ for (i = 0; i < fsl_dev->soc->total_layer; i++) {
+ for (j = 1; j <= reg_num; j++)
regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
}
regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,