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author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-06-20 18:57:52 +0300 |
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committer | Neil Armstrong <narmstrong@baylibre.com> | 2020-07-02 11:36:56 +0300 |
commit | 17f64701ea6f541db7eb5d7423a830cb929b3052 (patch) | |
tree | 9c058fbbf09ac8bc79902cf3fc77f27f3b785d51 /drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | |
parent | bda8eaa6dee7525f4dac950810a85a88bf6c2ba0 (diff) | |
download | linux-17f64701ea6f541db7eb5d7423a830cb929b3052.tar.xz |
drm/meson: viu: fix setting the OSD burst length in VIU_OSD1_FIFO_CTRL_STAT
The burst length is configured in VIU_OSD1_FIFO_CTRL_STAT[31] and
VIU_OSD1_FIFO_CTRL_STAT[11:10]. The public S905D3 datasheet describes
this as:
- 0x0 = up to 24 per burst
- 0x1 = up to 32 per burst
- 0x2 = up to 48 per burst
- 0x3 = up to 64 per burst
- 0x4 = up to 96 per burst
- 0x5 = up to 128 per burst
The lower two bits map to VIU_OSD1_FIFO_CTRL_STAT[11:10] while the upper
bit maps to VIU_OSD1_FIFO_CTRL_STAT[31].
Replace meson_viu_osd_burst_length_reg() with pre-defined macros which
set these values. meson_viu_osd_burst_length_reg() always returned 0
(for the two used values: 32 and 64 at least) and thus incorrectly set
the burst size to 24.
Fixes: 147ae1cbaa1842 ("drm: meson: viu: use proper macros instead of magic constants")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200620155752.21065-1-martin.blumenstingl@googlemail.com
Diffstat (limited to 'drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c')
0 files changed, 0 insertions, 0 deletions