diff options
| author | Lee Shawn C <shawn.c.lee@intel.com> | 2021-09-08 14:56:05 +0300 |
|---|---|---|
| committer | Vandita Kulkarni <vandita.kulkarni@intel.com> | 2021-09-08 17:04:39 +0300 |
| commit | fe01883fdcefd09c7ceb91874c2f74ae074163d6 (patch) | |
| tree | fc3903591abb5731f1a3dcfdbbf495c21b83aade /drivers/gpu/drm/i915/display/intel_cdclk.c | |
| parent | 5ebd50d3948ee596db02399a09b4561ed82aee57 (diff) | |
| download | linux-fe01883fdcefd09c7ceb91874c2f74ae074163d6.tar.xz | |
drm/i915: Get proper min cdclk if vDSC enabled
VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.
v2:
- Check for dsc enable and slice count ==1 then allow to
double confirm min cdclk value.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210908115607.9633-4-shawn.c.lee@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cdclk.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 34fa4130d5c4..9aec17b33819 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2140,6 +2140,16 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); /* + * VDSC engine can process only 1 pixel per Cd clock. + * In case VDSC is used and max slice count == 1, + * max supported pixel clock should be 100% of CD clock. + * Then do min_cdclk and pixel clock comparison to get cdclk. + */ + if (crtc_state->dsc.compression_enable && + crtc_state->dsc.slice_count == 1) + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); + + /* * HACK. Currently for TGL platforms we calculate * min_cdclk initially based on pixel_rate divided * by 2, accounting for also plane requirements, |