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authorImre Deak <imre.deak@intel.com>2018-08-28 15:22:31 +0300
committerImre Deak <imre.deak@intel.com>2018-08-29 13:21:52 +0300
commitd8c5d29f21bf0bc690fd8c26c54197221e235bc9 (patch)
tree24a749236cc2a2122ecfaed628a33781442543df /drivers/gpu/drm/i915/i915_gem.h
parent5df52391ddbed869c7d67b00fbb013bd64334115 (diff)
downloadlinux-d8c5d29f21bf0bc690fd8c26c54197221e235bc9.tar.xz
drm/i915: Don't check power domains state in intel_power_domains_init_hw()
During power domains initialization we acquire power well references for power wells in the INIT power domain. The rest of power wells - which BIOS could have left enabled - we can only acquire references as needed during display HW readout and so must defer sanitization until then (also implying that we must always do HW readout to cleanup unused power wells). Thus during initialization these latter power wells can have a refcount of 0 while still being enabled. To avoid the false-positive state mismatch error this causes remove the check from intel_power_domains_init_hw() and rely on the state check in intel_power_domains_enable() which follows the HW readout. v2: - Add comment to log and code clarifying how unused power wells get disabled. (Chris) Fixes: 6dfc4a8f134f ("drm/i915: Verify power domains after enabling them") Cc: Chris Wilson <chris@chris-wilson.co.uk> References: https://bugs.freedesktop.org/show_bug.cgi?id=107411 Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180828122231.14336-1-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.h')
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