diff options
| author | Eric Anholt <eric@anholt.net> | 2019-04-19 03:10:14 +0300 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2019-05-16 19:24:52 +0300 |
| commit | 38c2c7917adc8fb4ed9114b92923af9abe091af5 (patch) | |
| tree | 7d1ef7f05ad02bb7f5c7eaef80f5573ef5f404ee /drivers/gpu/drm/v3d/v3d_regs.h | |
| parent | 1ba9d7cbc4530ae35eb1ebbd3c5e59d0c587aefa (diff) | |
| download | linux-38c2c7917adc8fb4ed9114b92923af9abe091af5.tar.xz | |
drm/v3d: Fix and extend MMU error handling.
We were setting the wrong flags to enable PTI errors, so we were
seeing reads to invalid PTEs show up as write errors. Also, we
weren't turning on the interrupts. The AXI IDs we were dumping
included the outstanding write number and so they looked basically
random. And the VIO_ADDR decoding was based on the MMU VA_WIDTH for
the first platform I worked on and was wrong on others. In short,
this was a thorough mess from early HW enabling.
Tested on V3D 4.1 and 4.2 with intentional L2T, CLE, PTB, and TLB
faults.
Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419001014.23579-4-eric@anholt.net
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Diffstat (limited to 'drivers/gpu/drm/v3d/v3d_regs.h')
| -rw-r--r-- | drivers/gpu/drm/v3d/v3d_regs.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/v3d/v3d_regs.h b/drivers/gpu/drm/v3d/v3d_regs.h index eda1e289976f..9bcb57781d31 100644 --- a/drivers/gpu/drm/v3d/v3d_regs.h +++ b/drivers/gpu/drm/v3d/v3d_regs.h @@ -152,7 +152,8 @@ # define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19) # define V3D_MMU_CTL_PT_INVALID_INT BIT(18) # define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17) -# define V3D_MMU_CTL_WRITE_VIOLATION BIT(16) +# define V3D_MMU_CTL_PT_INVALID_ENABLE BIT(16) +# define V3D_MMU_CTL_WRITE_VIOLATION BIT(12) # define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11) # define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10) # define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9) |