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author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-02-22 09:22:46 +0300 |
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committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-05-02 02:07:08 +0300 |
commit | 1c7b8ed7dbe0f4601752a4e4ed46c9a78fd824a4 (patch) | |
tree | fa73c05c5f286d85b040fa0fe29c8c98d788c285 /drivers/gpu | |
parent | 5f12b42e538933b5ba71dd6da6cdd88afe1b13c8 (diff) | |
download | linux-1c7b8ed7dbe0f4601752a4e4ed46c9a78fd824a4.tar.xz |
drm/msm/dpu: drop INTF_EDP from interface type conditions
To remove possible confusion between (old) INTF_EDP and newer INTF_DP,
stop using INTF_EDP in DPU's code. Until the 8x74/8x84 SoCs are
supported by DPU driver, there is no point in using INTF_EDP.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/475560/
Link: https://lore.kernel.org/r/20220222062246.242577-5-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 21c8dd104908..2c14646661b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -92,8 +92,7 @@ static void drm_mode_to_intf_timing_params( } /* for DP/EDP, Shift timings to align it to bottom right */ - if ((phys_enc->hw_intf->cap->type == INTF_DP) || - (phys_enc->hw_intf->cap->type == INTF_EDP)) { + if (phys_enc->hw_intf->cap->type == INTF_DP) { timing->h_back_porch += timing->h_front_porch; timing->h_front_porch = 0; timing->v_back_porch += timing->v_front_porch; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 2ae30da7a9c7..3f4d2c6e1b45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -111,7 +111,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, /* read interface_cfg */ intf_cfg = DPU_REG_READ(c, INTF_CONFIG); - if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) + if (ctx->cap->type == INTF_DP) dp_intf = true; hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + |