diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-10-16 19:34:52 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:43:00 +0300 |
| commit | e12a64881e97a78694012646cabd211399db8753 (patch) | |
| tree | 8d833c37958a332cd33dbd478f2f816106d7f08a /drivers/gpu | |
| parent | de54bb81d9d43d0b66a63d839963e9d359e0467d (diff) | |
| download | linux-e12a64881e97a78694012646cabd211399db8753.tar.xz | |
drm/xe: Separate number of registers from MI_LRI opcode
Keeping the number of registers to be loaded as a separate macro from
the instruction opcode will simplify some upcoming LRC parsing code.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231016163449.1300701-10-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_lrc.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_ring_ops.c | 2 |
4 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h index 9432a960346b..ad1e5466671b 100644 --- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h +++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h @@ -25,9 +25,11 @@ #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) #define MI_STORE_DATA_IMM MI_INSTR(0x20, 0) -#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) +#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 0) #define MI_LRI_LRM_CS_MMIO REG_BIT(19) #define MI_LRI_MMIO_REMAP_EN REG_BIT(17) +#define MI_LRI_LENGTH GENMASK(5, 0) +#define MI_LRI_NUM_REGS(x) REG_FIELD_PREP(MI_LRI_LENGTH, 2 * (x) - 1) #define MI_LRI_FORCE_POSTED (1<<12) #define MI_FLUSH_DW MI_INSTR(0x26, 0) diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index c63e2e4750b1..a42ee3b9b8c7 100644 --- a/drivers/gpu/drm/xe/xe_gt.c +++ b/drivers/gpu/drm/xe/xe_gt.c @@ -145,7 +145,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) if (count) { xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name); - bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM(count); + bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); xa_for_each(&sr->xa, idx, entry) { struct xe_reg reg = entry->reg; diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c index 35ae6e531d8a..81463bd5e490 100644 --- a/drivers/gpu/drm/xe/xe_lrc.c +++ b/drivers/gpu/drm/xe/xe_lrc.c @@ -111,7 +111,7 @@ static void set_offsets(u32 *regs, flags = *data >> 6; data++; - *regs = MI_LOAD_REGISTER_IMM(count); + *regs = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); if (flags & POSTED) *regs |= MI_LRI_FORCE_POSTED; *regs |= MI_LRI_LRM_CS_MMIO; diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c index b95cc7713ff9..1e36b07d3e01 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops.c +++ b/drivers/gpu/drm/xe/xe_ring_ops.c @@ -50,7 +50,7 @@ static u32 preparser_disable(bool state) static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg, u32 *dw, int i) { - dw[i++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN; + dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN; dw[i++] = reg.addr + gt->mmio.adj_offset; dw[i++] = AUX_INV; dw[i++] = MI_NOOP; |