diff options
author | Prashant Laddha <prladdha@cisco.com> | 2015-06-10 19:51:42 +0300 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2015-07-06 14:25:49 +0300 |
commit | 5fea1bb703c360f323c62f6d34b5e947d0590e80 (patch) | |
tree | 4e642dc86404ba2441f412d6e5d9d035a5052c3d /drivers/media/platform/vivid/vivid-vid-cap.c | |
parent | 30533ad10b7c3d7c05b757382aee28458167ab75 (diff) | |
download | linux-5fea1bb703c360f323c62f6d34b5e947d0590e80.tar.xz |
[media] v4l2-dv-timings: add support for reduced blanking v2
Added support for reduced blanking version 2 (RB v2) in cvt timings.
Standard specifies a fixed vsync pulse of 8 lines to indicate RB v2
timings. Vertical back porch is fixed at 6 lines and vertical front
porch is remainder of vertical blanking time.
For RB v2, horizontal blanking is fixed at 80 pixels. Horizontal sync
is fixed at 32. All horizontal timing counts (active pixels, front,
back porches) can be specified upto a precision of 1.
RB v2 allows for non standard aspect ratios. In RB v2 vsync does not
indicate aspect ratio. In absence of aspect ratio v4l2_detect_cvt()
cannot calculate image width from image height. Hence extending the
v4l2_detect_cvt() to pass image width in case of RB v2.
Signed-off-by: Prashant Laddha <prladdha@cisco.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat (limited to 'drivers/media/platform/vivid/vivid-vid-cap.c')
-rw-r--r-- | drivers/media/platform/vivid/vivid-vid-cap.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/media/platform/vivid/vivid-vid-cap.c b/drivers/media/platform/vivid/vivid-vid-cap.c index c4268d1b2f82..ed0b8788a66f 100644 --- a/drivers/media/platform/vivid/vivid-vid-cap.c +++ b/drivers/media/platform/vivid/vivid-vid-cap.c @@ -1627,7 +1627,7 @@ static bool valid_cvt_gtf_timings(struct v4l2_dv_timings *timings) h_freq = (u32)bt->pixelclock / total_h_pixel; if (bt->standards == 0 || (bt->standards & V4L2_DV_BT_STD_CVT)) { - if (v4l2_detect_cvt(total_v_lines, h_freq, bt->vsync, + if (v4l2_detect_cvt(total_v_lines, h_freq, bt->vsync, bt->width, bt->polarities, bt->interlaced, timings)) return true; } |