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authortianshuliang <tianshuliang@hisilicon.com>2018-03-08 04:01:34 +0300
committerUlf Hansson <ulf.hansson@linaro.org>2018-03-15 16:43:22 +0300
commite382ab741252471383e9990583258e3054f66963 (patch)
tree176a5b0d8e1c5fcd1a2ed5c51a3a15bb103e29f1 /drivers/mmc/host/dw_mmc.h
parent8a9cdf985258d3409e5647fbcb8a573da35ee4f8 (diff)
downloadlinux-e382ab741252471383e9990583258e3054f66963.tar.xz
mmc: dw_mmc: add support for hi3798cv200 specific extensions of dw-mshc
Hi3798CV200 SoC extends the dw-mshc controller for additional clock and bus control. Add support for these extensions. Signed-off-by: tianshuliang <tianshuliang@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/dw_mmc.h')
-rw-r--r--drivers/mmc/host/dw_mmc.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 950f194e1573..46e9f8ec5398 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -314,6 +314,7 @@ struct dw_mci_board {
#define SDMMC_BUFADDR 0x098
#define SDMMC_CDTHRCTL 0x100
#define SDMMC_UHS_REG_EXT 0x108
+#define SDMMC_DDR_REG 0x10c
#define SDMMC_ENABLE_SHIFT 0x110
#define SDMMC_DATA(x) (x)
/*
@@ -439,7 +440,12 @@ struct dw_mci_board {
#define SDMMC_CARD_WR_THR_EN BIT(2)
#define SDMMC_CARD_RD_THR_EN BIT(0)
/* UHS-1 register defines */
+#define SDMMC_UHS_DDR BIT(16)
#define SDMMC_UHS_18V BIT(0)
+/* DDR register defines */
+#define SDMMC_DDR_HS400 BIT(31)
+/* Enable shift register defines */
+#define SDMMC_ENABLE_PHASE BIT(0)
/* All ctrl reset bits */
#define SDMMC_CTRL_ALL_RESET_FLAGS \
(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)